Value Set
The Verilog HDL value set consists of four basic values:
0 - represents a logic zero, or a false condition
1 - represents a logic one, or a true condition
x - represents an unknown logic value
z - represents a high-impedance state
The values 0 and 1 are logical complements of one another.
Net
The net data types shall represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate. If no driver is connected to a net, its value shall be high-impedance (z) unless the net is a trireg, in which case it shall hold the previously driven value. It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
Variable Or Reg
A variable is an abstraction of a data storage element. A variable shall store a value from one assignment to the next. An assignment statement in a procedure acts as a trigger that changes the value in the data storage element. The initialization value for reg, time, and integer data types shall be the unknown value, x. The default initialization value for real and realtime variable datatypes shall be 0.0. If a variable declaration assignment is used , the variable shall take this value as if the assignment occurred in a blocking assignment in an initial construct. It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
Vectors
A net or reg declaration without a range specification shall be considered 1 bit wide and is known as a scalar. Multiple bit net and reg data types shall be declared by specifying a range, which is known as a vector.
EXAMPLES:
wand w; // a scalar net of type wand
tri [15:0] busa; // a three-state 16-bit bus
trireg (small) storeit; // a charge storage node of strength small
reg a; // a scalar reg
reg[3:0] v; // a 4-bit vector reg made up of (from most to
// least significant) v[3], v[2], v[1], and v[0]
reg signed [3:0] signed_reg; // a 4-bit vector in range -8 to 7
reg [-1:4] b; // a 6-bit vector reg
wire w1, w2; // declares two wires
reg [4:0] x, y, z; // declares three 5-bit regs
Memories
A one dimensional array with elements of type reg is also called a memory. These memories can be used to model read-only memories (ROMs), random access memories (RAMs), and reg files. Each reg in the array is known as an element or word and is addressed by a single array index. An n-bit reg can be assigned a value in a single assignment, but a complete memory cannot. To assign a value to a memory word, an index shall be specified. The index can be an expression. This option provides a mechanism to reference different memory words, depending on the value of other variables and nets in the circuit. For example, a program counter reg could be used to index into a RAM.
EXAMPLE:
reg [7:0] mema[0:255]; // declares a memory mema of 256 8-bit
// registers. The indices are 0 to 255
reg arrayb[7:0][0:255]; // declare a two dimensional array of
// one bit registers
wire w_array[7:0][5:0]; // declare array of wires
integer inta[1:64]; // an array of 64 integer values
time chng_hist[1:1000] // an array of 1000 time values
mema = 0; // Illegal syntax- Attempt to write to entire array
arrayb[1] = 0; // Illegal Syntax - Attempt to write to elements
// [1][0]..[1][255]
arrayb[1][12:31] = 0; // Illegal Syntax - Attempt to write to
// elements [1][12]..[1][31]
mema[1] = 0; //Assigns 0 to the second element of mema
arrayb[1][0] = 0; // Assigns 0 to the bit referenced by indices
// [1][0]
inta[4] = 33559; // Assign decimal number to integer in array
chng_hist[t_index] = $time; // Assign current simulation time to
// element addressed by integer index
reg [1:n] rega; // An n-bit register is not the same
reg mema [1:n]; // as a memory of n 1-bit registers
Net Types
There are several distinct types of nets , they are
wire , tri , tri0 , supply0 , wand, triand, tri1, supply1, wor, trior, trireg.
The Verilog HDL value set consists of four basic values:
0 - represents a logic zero, or a false condition
1 - represents a logic one, or a true condition
x - represents an unknown logic value
z - represents a high-impedance state
The values 0 and 1 are logical complements of one another.
Net
The net data types shall represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate. If no driver is connected to a net, its value shall be high-impedance (z) unless the net is a trireg, in which case it shall hold the previously driven value. It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
Variable Or Reg
A variable is an abstraction of a data storage element. A variable shall store a value from one assignment to the next. An assignment statement in a procedure acts as a trigger that changes the value in the data storage element. The initialization value for reg, time, and integer data types shall be the unknown value, x. The default initialization value for real and realtime variable datatypes shall be 0.0. If a variable declaration assignment is used , the variable shall take this value as if the assignment occurred in a blocking assignment in an initial construct. It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
Vectors
A net or reg declaration without a range specification shall be considered 1 bit wide and is known as a scalar. Multiple bit net and reg data types shall be declared by specifying a range, which is known as a vector.
EXAMPLES:
wand w; // a scalar net of type wand
tri [15:0] busa; // a three-state 16-bit bus
trireg (small) storeit; // a charge storage node of strength small
reg a; // a scalar reg
reg[3:0] v; // a 4-bit vector reg made up of (from most to
// least significant) v[3], v[2], v[1], and v[0]
reg signed [3:0] signed_reg; // a 4-bit vector in range -8 to 7
reg [-1:4] b; // a 6-bit vector reg
wire w1, w2; // declares two wires
reg [4:0] x, y, z; // declares three 5-bit regs
Memories
A one dimensional array with elements of type reg is also called a memory. These memories can be used to model read-only memories (ROMs), random access memories (RAMs), and reg files. Each reg in the array is known as an element or word and is addressed by a single array index. An n-bit reg can be assigned a value in a single assignment, but a complete memory cannot. To assign a value to a memory word, an index shall be specified. The index can be an expression. This option provides a mechanism to reference different memory words, depending on the value of other variables and nets in the circuit. For example, a program counter reg could be used to index into a RAM.
EXAMPLE:
reg [7:0] mema[0:255]; // declares a memory mema of 256 8-bit
// registers. The indices are 0 to 255
reg arrayb[7:0][0:255]; // declare a two dimensional array of
// one bit registers
wire w_array[7:0][5:0]; // declare array of wires
integer inta[1:64]; // an array of 64 integer values
time chng_hist[1:1000] // an array of 1000 time values
mema = 0; // Illegal syntax- Attempt to write to entire array
arrayb[1] = 0; // Illegal Syntax - Attempt to write to elements
// [1][0]..[1][255]
arrayb[1][12:31] = 0; // Illegal Syntax - Attempt to write to
// elements [1][12]..[1][31]
mema[1] = 0; //Assigns 0 to the second element of mema
arrayb[1][0] = 0; // Assigns 0 to the bit referenced by indices
// [1][0]
inta[4] = 33559; // Assign decimal number to integer in array
chng_hist[t_index] = $time; // Assign current simulation time to
// element addressed by integer index
reg [1:n] rega; // An n-bit register is not the same
reg mema [1:n]; // as a memory of n 1-bit registers
Net Types
There are several distinct types of nets , they are
wire , tri , tri0 , supply0 , wand, triand, tri1, supply1, wor, trior, trireg.
